Iwai Lab

●2011年発表

Science China, Vol.54, No.5, pp. 1004-1011, May 2011
“Si nanowire FET and its modeling”

●2007年発表

Japanese Journal of Applied Physics, Vol.46, No.16, 2007 pp.L376-L378
“Characteristics of Ultrathin Lanthanum Oxide Films on Germanium Substrate: Comparison with Those on Silicon Substrate”

●2006年発表

IWJT-2006
"Irregular Increase in sheet Resistance of Ni Sikicides at Temperature Range of Transition from NiSi to NiSi2"

2006ECS
"New Theory of Effective Work Functions at Metal/High-k Dielectric Interfaces-Application to Metal/High-k HfO2 And La2O3 Dielectric Interfaces-z"
"Combinatorial Fabrication and Characterization of Oxide and Metal Thin Film Composition Spreads"
"Lanthanum Oxides for Gate Insulator Application
Angle-Resolved Photoelectron Spectroscopy Study on Gate Insulators"
"Mobility Degradation Analysis for La2O3 nMOSFET"

2006VLSI-TSA
"Semiconductor Manufacturing Technology in the 21st Century"

2006-IWNE
"CMOS Scaling and Future Manufacturin"

ISTC-2006
"Photo Resist Removal Process UIsing Wet Treatment After Plasma Doping"
"Formation of Ultra-shallow Junctions by Plasma Doping
Analysis of Voltage Coefficient and Leakage Current of La2O3 Mim Capacitor"
"Combinatorial Fabrication and Phase Diagramming of Ternary Composition Spreads"

IWNC
"Recent Status an Nano CMOS and Future Direction"

IEEE LEOS Chapter& EDS Chapter
"Future of CMOS and Its Manufacturing"

EPMDS-2006
"Future CMOS Technology and Manufacturing"

●2005年発表

IWPSD-2005
Future of CMOS Scaling and Its Manufacturing

IEEE EDS WIMNACT-9
CMOS Scaling and its Future towards Downsizing Limit

VLSI 2005
Silicon Integrated Circit Technology and MANUFACTURING Innobations for the Past and the Next 30 Years

ESSDERC 2005
The Effect of Y2O3 Buffer Layer for La2O3 Gate Dielectric Film
RF Modeling of Sub‐100 nm CMOS
High-K Gate Stack Technology

IWJT 2005
Feasibility Study of Plasma Doping on Si Substrates with Photo-Resist Patterns
Analysis of Conductivity in Ultra-shallow p+ Layers Formed by Plasma Doping
Reverse Current of Plasma Doped p+/n Ultra-Shallow Junction

SEMANTEC 2005
Challenges for the CMOS Roadmap and Nanotechnology beyond CMOS

6th Workshop and IEEE EDS Mini-colloquia on Nanometer CMOS Technology
New Technology Study for Future Downscaling CMOS: High-k and Plasma Doping

●2004年発表

WOFE 2004
Challenges for Future Semiconductor Manufacturing

2004 IEDM
Futre Semiconductor Manufactureing-Challenges and Opportunities

ICCDCS 2004
CMOS Technology Future

2004 Semiconductor Manufacturing Tecnology workshop Proceedings
Future of CMOS Technology

2004APRASC
RF CMOS Technology

MIXDES 2004
Future CMOS Scaling

VLSI 2004
CMOS Scaling for sub-90 nm to sub-10nm

CODEC 04
CMOS Scaling Challenge to sub-10nm

●2003年発表

IWPSD 2003
Scaling of Advanced CMOS

EDMO 2003
Scaling of Advanced CMOS

Journal of Vacuum Science & Technology B (JVST B)
Dry etching characteristics of TiN film using Ar/CHF₃, Ar/Cl₂, and Ar/BCl₃ gas chemistries in an inductively coupled plasma

IUMRS-ICAM 2003
CMOS Downscaling

ESSDERC 2003
Advanced High K Dielectrics

応用物理　巻頭言Vol72, No.9
「微細化の末法時代とはーシリコンデバイスの重要性とその行方ー」

半導体技術・産業の未来2003年版（日経マイクロデバイス特別編集版）
全15種類の希土類材料薄膜を調査　次世代ゲート絶縁膜へ応用

SolidState Technology,Vol.2003-06
High-tilt implant and diffusion-less activation for lateral graded S/D engineering

FTM(Future Trends in Microelectronics)-2003
The Future of CMOS Downscaling

INFOS 2003
Composition, Chemical Structure and Electronic Band Structure of
Rare Earth Oxide/Si(100) Interfacial Transition Layer

電子情報通信学会論文誌
巻頭言：シリコンデバイスの40年と日本

International Symposium on Plasma and Process -Induced Damage
CMOS Down Scaling and Process Induced Damages

2003 MRS Spring Meeting
Prospects and Challenges for Advanced Gate-Stack Materials in Sub-65nm CMOS

ULIS2003
CMOS Downsizing toward sub-10nm

●2002年発表

文部科学省科学技術政策研究所
日本にとってのシリコン半導体デバイス研究開発の重要性とその戦略（講演録）

酸化膜研究会
50nm以下の領域へのCMOSのスケーリングとそのための必要プロセス技術
CMOS Scaling towards sub-50 nm and Required Process Technologies

IEDM 2002
Advanced Gate Dielectric Materials for Sub-100nm CMOS

SISC 2002
CMOS Scaling and Requested New Technologies

ECS 202nd Meeting
High Dielectric Constant Gate Insulator Technology using Rare Earth Oxides

IEEE EDS ED 2002
CMOS Downscaling Towards Its Limit

ESREF 2002
Trend of CMOS downsizing and its reliability

SSDM
Electrical Characteristics of Rare Earth Gate Oxides Improved by Chemical Oxide and Long Low Temperature Annealing

ISTC
Characterization of Lu2O3 High-k Thin Films on Si(100) Fabricated by E-beam Deposition Method

STARCシンポジウム2002
Trend of Sub-70nm High-Speed CMOS Devices and Expected Problems

ICD-SDM(函館）
低消費電力化技術とゲート絶縁膜の薄膜化

ICCDCS 2002
CMOS DOWNSIZING AND HIGH-K GATE INSULATOR TECHNOLOGY

●2001年発表

Break Through 12月号
Suｂ-10mm　CMOSへの挑戦

プレスジャーナル
High-kゲート絶縁膜実用化に向けての課題

Material for Advanced Metallization
March 5-7,2001 Sigtuna-Sweden
NiSi Salicide Technology for Scaled CMOS

●2000年発表

『応用物理』第69巻第1号（2000年）
微細シリコンデバイスに要求される各種高性能薄膜

2000年12月 ELECTRON DEVICES VOL.47,No.12
An Accurate and Efficient High Frequency Noise Simulation Technique for Deep Submicron MOSFETs

2000年12月 ELECTRON DEVICES VOL.47,No.12
Power Si-MOSFET Operating with High Efficiency Under Low Supply Voltage

2000年2月ISSS 2000, India
"Sub-100 nm MOSFET Technologies

2000年1月東北大学電気通信研究所共同プロジェクト研究
｢微細デバイスと配線技術｣

●1999年発表

1999年12月IEDM Short Course(Washington DC)
"Source Drain and Wells" in Sub-100nm CMOS"

1999年7月 ELECTRON DEVICES VOL.46,No.7
An 0.18-nm CMOS for Mixed Digital and Analog Applications with Zero-Volt-V_th Epitaxial-Channel MOSFET's

1999年4月 ELECTRON DEVICES VOL.46,No.4
An 0.3-nm Si Epitaxial Base BiCMOS Technology with 37-GHz f_max and 10-V BV_ceo for RF Telecommunication

Solid State Electronics, vol.43, no.7, pp.1219-1224
"A study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation"

Solid State Electronics, vol.43 no.7, pp.1209-1214
"A high performance 0.15 μm buried channel pMOSFET with extremel shallow counter doped channel region using solid phase diffusion"

Microelectronic Engineering, vol.48, pp.7-14
"Outlook of MOS Devices into Next Century"

IEEE Transactions on Electron Devices, vol.46, pp.1378-1383
"An 0.18-μm CMOS for Mixed Digital and Analog Applications with Zero-Volt-Vth Epitaxial-Channel MOSFET's"

IEEE Trans. Electron Devices, vol. 46, pp.712-721
“ An 0.3-mm Si epitaxial base BiCMOS technology with 37-GHz fmax and 10-V Bceo for RF telecommunication,

IEEE Journal of Solid-State Circuits, vol.34, pp.357-366
“CMOS Technology - Year 2010 and beyond”

Solid-State Electronics, vol.43, pp.543-546
“Single-gate 0.15 and 0.12 mm CMOS with Co salicide technology,”

●1998年発表

1998年6月 ELECTRON DEVICES VOL.45,No.6
High Performance of Silicided Silicon-Sidewall Source and Drain (S⁴D)Structure

1998年6月 ELECTRON DEVICES VOL.45,No.6
High Efficiency and High Linearity InGaP/GaAs HBT Power Amplifiers： Matching Techniques of Source and Load Impedance to Improve Phase Distortion and Linearity

1998年3月 ELECTRON DEVICES VOL.45,No.3
0.15-nm RF CMOS Technology Compatible with Logic CMOS for Low-Voltage Operation

1998年3月 ELECTRON DEVICES VOL.45,No.3
0.15-nm Buried-Channel p-MOSFET's with Ultrathin Boron-Doped Epitaxial Si Layer

1998年3月 ELECTRON DEVICES VOL.45,No.3
Updoped Epitaxial Si Channel n-MOSFET Grown by UHV-CVD with Preheating

1998年3月 ELECTRON DEVICES VOL.45,No.3
Study of Manufacturing Feasiblity of 1.5-nm Direct-Tunneling Gate Oxide MOSFET's: Uniformity, Reliability, and Dopant Penetration of the Gate Oxide

Microelectronics Reliability, vol.38, pp.1413-1423
“Application of direct-tunneling gate oxides to high-performance CMOS,”

IEEE Trans. Electron Devices, vol. 45, pp.1295-1299 (1998)
“High performance of silicided silicon-sidewall source and drain (S4D) structure,”

Microelectronics Journal, vol.29, pp.671-678
“Downsizing of silicon MOSFETs beyond 0.1 mm,”

IEEE Trans. Electron Devices, vol. 45, pp.737-742
”0.15-mm RF CMOS technology compatible with logic CMOS for low-voltage operation”

IEEE Trans. Electron Devices, vol. 45, pp.717-721
”A 0.15-mm buried-channel p-MOSFET’s with ultrathin boron-doped epitaxial Si layer,”

IEEE Trans. Electron Devices, vol. 45, pp.710-716
”Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating,”

IEEE Trans. Electron Devices, vol. 45, pp.691-700
”Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFET’s: Uniformity, reliability, and dopant penetration of the gate oxide,”

IEICE Trans. on Fundamentals, vol.E81-A, pp.382-388
“A 1.5GHZ CMOS low noise amplifier”

●1997年発表

1997年11月 ELECTRON DEVICES VOL.44,No.11
A Hot-Carrier Degradation Mechanism and Electrical Characteristics in S⁴D n-MOSFET's

IEEE Trans. Electron Devices, vol. 44, pp.2053-2058
“A hot-carrier degradation mechanism and electrical charateristics in of S4D n-MOSFETs,”

Microelectronic Engineering, vol.39 pp.7-30
“Technology toward low power / low voltage and scaling of MOSFETs”

Solid-State Electronics Vol.41, pp. 707-714
"Prospects for Low-power, High-speed MPUs Using 1.5 nm Direct-tunneling Gate Oxide MOSFETs,"

IEEE Trans. Electron Devices, vol. 43, pp.1233-1242,
"1.5 nm Direct-Tunneling Gate Oxide Si MOSFET's,"

●1996年発表

Electronics and Communication in Japan, Part 2, vol.79, pp.67-76
”Realization of High-Performance MOSFETs with gate lengths of 0.1 mm or Less,”

Electronics and Communication in Japan, Part 2, vol.79, pp.67-76 (1996)
”Realization of High-Performance MOSFETs with gate lengths of 0.1 mm or Less,”

●1995年発表

IEEE Trans. Electron Devices, vol. 42, pp.1822-1830
"A 40 nm gate length n-MOSFET,"

IEEE Trans. Electron Devices, vol. 42, pp.1510-1521
"A Study on Hot Carrier Effects on N-MOSFET's Under High Substrate Impurity Concentration,"

J. Vac. Sci. Technol., vol.B13, pp.1740-1743
M"Fabrication of sub-50-nm gate length n-metal-oxide semiconductor field effect transistors and their electrical characteristics,"

Microelectronic Engineering, vol.28 pp.147-154
"The future of ultra-small-geometry MOSFETs beyond 0.1 micron,"

IEEE Trans. Electron Devices, vol. 42, pp.915-922
"Self-Aligned Nickel-Mono-Silicide Technology for High-Speed Deep Submicrometer Logic CMOS ULSI,"

IEEE Trans. Electron Devices, vol. 42, pp.704-712
"An Improvement of Hot-Carrier Reliability in the Stacked Nitride-Oxide Gate n- and p-MISFET's,"

IEEE Trans. Electron Devices, vol. 42, pp.399-405
"Sub-20 ps High-Speed ECL Bipolar Transistor with Low Parasitic Architecture,"

●1994年発表

IEEE Trans. Electron Devices, vol. 41, pp.2305-2317
"Analysis of Resistance Behavior in Ti- and Ni- Salicided Polysilicon Films,"

IEEE Trans. Electron Devices, vol. 41, pp.941-951
"Scaling the MOS transistor below 0.1 mm: methodology, device structures and technology requirements,"

IEEE Trans. Electron Devices, vol. 41, pp.978-987 (1994)
"Analysis of the Temperature Dependence of Hot-Carrier-Induced Degradation in Bipolar Transistors for Bi-CMOS,"

IEEE Trans. Electron Devices, vol. 41, pp.546-552 (1994)
"Electrical Characteristics of Rapid Thermal Nitride-Oxide Gate n- and p-MOSFET's with Less Than 1 Atom% Nitrogen Concentration,"

●1993年発表

IEICE Trans. Electron., vol.E77-C, pp.174-178
"Monte Carlo Analysis of Velocity Overshoot Effects in Bipolar Devices with and without an i-Layer,"

IEICE Trans. Electron., vol.E77-C, pp.124-128 ( 1993).
"Mechanical Stress Analysis of Trench Isolation Using a Two-Dimensional Simulation,"

IEEE Trans. Electron Devices, vol.ED-40, no.12, pp.2264-2272
"P-MOSFET's with Ultra-Shallow Solid-Phase-Diffused Drain Structure Produced by Diffusion from BSG Gate-Sidewall,"

IEEE Trans. Electron Devices, vol. 40, pp.1768-1779
"New Charge Pumping Method for Determining the Spatial Distribution of Hot-Carrier-Induced Fixed Charge in p-MOSFET's,"

IEEE Trans. Electron Devices, vol. 40, pp.371-377
"A new contact plug technique for deep-submicron ULSIs employing selective nickel silicidation of polysilicon with a titanium nitride stopper,"

●1992年発表

1992年6月 VLSI Symposium on Technology, Siattle, Washington, pp.70-71
"A novel selective Ni3Si contact plug technique for deep-submicron ULSIs,"

IEEE Trans. Electron Devices, vol.39, pp.648-661
"A study of non-equilibrium diffusion modeling; Application to rapid thermal annealing and advanced bipolar technologies,"

IEEE Trans. Electron Devices, vol.39, pp.33-40, January
"Impurity diffusion behaviors of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5 mm Bi-CMOS process,"

●1991年発表

H. Iwai, "Hot carrier induced degradation mode in thin gate insulator dual gate MISFETs,", Edited by W. Eccleston and M. Uren, "Insulating Films on Semiconductors 1991," Adam Hilger, Bristol, Philadelphia and New York, pp.83-92

●1990年発表

IEEE Trans. Electron Devices, vol.37, pp.1496-1503
"Analysis of gate oxide thickness dependence of hot carrier induced degradation in thin gate oxide nMOSFETs,"

IEEE Trans. Electron Devices, vol. 37, pp.1487-1495
"Analysis of hot carrier induced degradation mode on PMOSFETs,"

IEEE Trans. Electron Devices, vol.37, pp.562-568
"Electromigration reliability for tungsten filled via hole structure,"

●1989年発表

IEEE Trans. Electron Devices, vol.36, pp.1732-1739
"Interface state generation under long term positive bias temperature stress for a p+ poly gate MOS structure,"

●1988年発表

"1.2 mm Bi-CMOS technology with high performance ECL," Solid State Devices, edited by E. Soncini and P. U. Calzolari, Elsevier Science Publishers B. V. (North-Holland), pp.199-202 ●1987年発表

IEEE J. Solid-State Circuits, vol.22, pp.733-740
M "A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines,"

IEEE Trans. Computer-Aided Design, vol.6, pp.173-184
H. Iwai, M. R. Pinto, C. S. Raffrety, J. E. Oristian, and R. W. Dutton, "Analysis of velocity saturation and other effects on short channel MOS transistor capacitances,"

●1985年発表

IEEE Trans. Electron Devices, vol. ED-32, pp.344-356
"A scaleable technique for measurement of intrinsic MOS capacitance with atto Farad resolution,"

1985年1月IEEE Electron Device Letters, vol.EDL-6, No.1
"A reply to "Comments to `Small geometry MOS transistor capacitance measurement method using simple on-chip circuits"

1985年3月IEEE Electron Device Letters, vol.EDL-6, No.3, pp.120-122
"Velocity saturation effect on short channel MOS transistor capacitance,"

●1984年発表

IEEE Trans. Electron Devices, vol.31, pp.1149-1151
"Comparison of intrinsic gettering and epitaxial wafers in terms of soft error endurance and other characteristics of 64k bit dynamic RAM,"

1984年10月IEEE Electron Device Letters, vol.EDL-5, No.10, pp.395-397
"Small geometry MOS transistor capacitance measurement method using simple on-chip circuits,"

●1982年発表

IEEE Trans. Electron Devices, vol. 29, pp. 1622-1626
"On-chip capacitance measurement circuits in VLSI structures,"

IEEE Trans. Electron Devices, vol.29, pp.625-630
"Two-dimensional nature of diffused layers and certain limitations in scaling-down coplanar structure,"

IEEE Electron Device Letters, vol. EDL-3, No.7, pp.182-184
"The effect of substrate materials on holding time degradation in MOS dynamic RAM,"

●1981年発表

IEEE Trans. on Electron Devices, vol.28, pp.574-580
"Two-dimensional computer simulation models for MOSLSI fabrication processes,"

IEEE Trans. Electron Devices, vol.28, pp116-117
L. M. Dang and H. Iwai, "Modeling of the impurity profile in an ion-implanted layer of an IGFET for the calculation of threshold voltages,"

●1980年発表

Japan J. Appl. Phys.vol.19, Suppl. 19-1, pp.107-112
"P-channel versus N-channel in MOS-ICs of submicron channel lengths,"

Toshiba Review, No.128, pp.35-38
"64k-bit dynamic RAM TMM4164C,"

●1979年発表

Japan J. Appl. Phys. vol.
M. Konaka, H. Iwai, and Y. Nishi, "Suppression of anomalous drain current in short channel MOSFET,"

IEEE J. Solid-State Circuits, vol. 14, pp.482-485
"A 64k bit MOS dynamic random access memory,"

●1976年発表

Japan J. Appl. Phys., vol.15 pp.63-69
"Micro-probe Auger analysis of Si migration in Al metallization for LSI,"


	TOP 御挨拶研究内容研究ニュース岩井教授研究業績岩井教授略歴論文一覧最近の発表学会活動受賞研究室志望の方へ研究室へのお客様スタッフ紹介アルバムリンク集アクセス東京工業大学フロンティア研究センター岩井研究室 TEL:045-924-5471 FAX:045-924-5584 最終更新日:2011.5.30		岩井教授論文一覧 ●2011年発表 Science China, Vol.54, No.5, pp. 1004-1011, May 2011 “Si nanowire FET and its modeling” ●2007年発表 Japanese Journal of Applied Physics, Vol.46, No.16, 2007 pp.L376-L378 “Characteristics of Ultrathin Lanthanum Oxide Films on Germanium Substrate: Comparison with Those on Silicon Substrate” ●2006年発表 IWJT-2006 "Irregular Increase in sheet Resistance of Ni Sikicides at Temperature Range of Transition from NiSi to NiSi2" 2006ECS "New Theory of Effective Work Functions at Metal/High-k Dielectric Interfaces-Application to Metal/High-k HfO2 And La2O3 Dielectric Interfaces-z" "Combinatorial Fabrication and Characterization of Oxide and Metal Thin Film Composition Spreads" "Lanthanum Oxides for Gate Insulator Application Angle-Resolved Photoelectron Spectroscopy Study on Gate Insulators" "Mobility Degradation Analysis for La2O3 nMOSFET" 2006VLSI-TSA "Semiconductor Manufacturing Technology in the 21st Century" 2006-IWNE "CMOS Scaling and Future Manufacturin" ISTC-2006 "Photo Resist Removal Process UIsing Wet Treatment After Plasma Doping" "Formation of Ultra-shallow Junctions by Plasma Doping Analysis of Voltage Coefficient and Leakage Current of La2O3 Mim Capacitor" "Combinatorial Fabrication and Phase Diagramming of Ternary Composition Spreads" IWNC "Recent Status an Nano CMOS and Future Direction" IEEE LEOS Chapter& EDS Chapter "Future of CMOS and Its Manufacturing" EPMDS-2006 "Future CMOS Technology and Manufacturing" ●2005年発表 IWPSD-2005 Future of CMOS Scaling and Its Manufacturing IEEE EDS WIMNACT-9 CMOS Scaling and its Future towards Downsizing Limit VLSI 2005 Silicon Integrated Circit Technology and MANUFACTURING Innobations for the Past and the Next 30 Years ESSDERC 2005 The Effect of Y2O3 Buffer Layer for La2O3 Gate Dielectric Film RF Modeling of Sub‐100 nm CMOS High-K Gate Stack Technology IWJT 2005 Feasibility Study of Plasma Doping on Si Substrates with Photo-Resist Patterns Analysis of Conductivity in Ultra-shallow p+ Layers Formed by Plasma Doping Reverse Current of Plasma Doped p+/n Ultra-Shallow Junction SEMANTEC 2005 Challenges for the CMOS Roadmap and Nanotechnology beyond CMOS 6th Workshop and IEEE EDS Mini-colloquia on Nanometer CMOS Technology New Technology Study for Future Downscaling CMOS: High-k and Plasma Doping ●2004年発表 WOFE 2004 Challenges for Future Semiconductor Manufacturing 2004 IEDM Futre Semiconductor Manufactureing-Challenges and Opportunities ICCDCS 2004 CMOS Technology Future 2004 Semiconductor Manufacturing Tecnology workshop Proceedings Future of CMOS Technology 2004APRASC RF CMOS Technology MIXDES 2004 Future CMOS Scaling VLSI 2004 CMOS Scaling for sub-90 nm to sub-10nm CODEC 04 CMOS Scaling Challenge to sub-10nm ●2003年発表 IWPSD 2003 Scaling of Advanced CMOS EDMO 2003 Scaling of Advanced CMOS Journal of Vacuum Science & Technology B (JVST B) Dry etching characteristics of TiN film using Ar/CHF₃, Ar/Cl₂, and Ar/BCl₃ gas chemistries in an inductively coupled plasma IUMRS-ICAM 2003 CMOS Downscaling ESSDERC 2003 Advanced High K Dielectrics 応用物理　巻頭言Vol72, No.9 「微細化の末法時代とはーシリコンデバイスの重要性とその行方ー」半導体技術・産業の未来2003年版（日経マイクロデバイス特別編集版）全15種類の希土類材料薄膜を調査　次世代ゲート絶縁膜へ応用 SolidState Technology,Vol.2003-06 High-tilt implant and diffusion-less activation for lateral graded S/D engineering FTM(Future Trends in Microelectronics)-2003 The Future of CMOS Downscaling INFOS 2003 Composition, Chemical Structure and Electronic Band Structure of Rare Earth Oxide/Si(100) Interfacial Transition Layer 電子情報通信学会論文誌巻頭言：シリコンデバイスの40年と日本 International Symposium on Plasma and Process -Induced Damage CMOS Down Scaling and Process Induced Damages 2003 MRS Spring Meeting Prospects and Challenges for Advanced Gate-Stack Materials in Sub-65nm CMOS ULIS2003 CMOS Downsizing toward sub-10nm ●2002年発表文部科学省科学技術政策研究所日本にとってのシリコン半導体デバイス研究開発の重要性とその戦略（講演録）酸化膜研究会 50nm以下の領域へのCMOSのスケーリングとそのための必要プロセス技術 CMOS Scaling towards sub-50 nm and Required Process Technologies IEDM 2002 Advanced Gate Dielectric Materials for Sub-100nm CMOS SISC 2002 CMOS Scaling and Requested New Technologies ECS 202nd Meeting High Dielectric Constant Gate Insulator Technology using Rare Earth Oxides IEEE EDS ED 2002 CMOS Downscaling Towards Its Limit ESREF 2002 Trend of CMOS downsizing and its reliability SSDM Electrical Characteristics of Rare Earth Gate Oxides Improved by Chemical Oxide and Long Low Temperature Annealing ISTC Characterization of Lu2O3 High-k Thin Films on Si(100) Fabricated by E-beam Deposition Method STARCシンポジウム2002 Trend of Sub-70nm High-Speed CMOS Devices and Expected Problems ICD-SDM(函館）低消費電力化技術とゲート絶縁膜の薄膜化 ICCDCS 2002 CMOS DOWNSIZING AND HIGH-K GATE INSULATOR TECHNOLOGY ●2001年発表 Break Through 12月号 Suｂ-10mm　CMOSへの挑戦プレスジャーナル High-kゲート絶縁膜実用化に向けての課題 Material for Advanced Metallization March 5-7,2001 Sigtuna-Sweden NiSi Salicide Technology for Scaled CMOS ●2000年発表『応用物理』第69巻第1号（2000年）微細シリコンデバイスに要求される各種高性能薄膜 2000年12月 ELECTRON DEVICES VOL.47,No.12 An Accurate and Efficient High Frequency Noise Simulation Technique for Deep Submicron MOSFETs 2000年12月 ELECTRON DEVICES VOL.47,No.12 Power Si-MOSFET Operating with High Efficiency Under Low Supply Voltage 2000年2月ISSS 2000, India "Sub-100 nm MOSFET Technologies 2000年1月東北大学電気通信研究所共同プロジェクト研究｢微細デバイスと配線技術｣ ●1999年発表 1999年12月IEDM Short Course(Washington DC) "Source Drain and Wells" in Sub-100nm CMOS" 1999年7月 ELECTRON DEVICES VOL.46,No.7 An 0.18-nm CMOS for Mixed Digital and Analog Applications with Zero-Volt-V_th Epitaxial-Channel MOSFET's 1999年4月 ELECTRON DEVICES VOL.46,No.4 An 0.3-nm Si Epitaxial Base BiCMOS Technology with 37-GHz f_max and 10-V BV_ceo for RF Telecommunication Solid State Electronics, vol.43, no.7, pp.1219-1224 "A study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation" Solid State Electronics, vol.43 no.7, pp.1209-1214 "A high performance 0.15 μm buried channel pMOSFET with extremel shallow counter doped channel region using solid phase diffusion" Microelectronic Engineering, vol.48, pp.7-14 "Outlook of MOS Devices into Next Century" IEEE Transactions on Electron Devices, vol.46, pp.1378-1383 "An 0.18-μm CMOS for Mixed Digital and Analog Applications with Zero-Volt-Vth Epitaxial-Channel MOSFET's" IEEE Trans. Electron Devices, vol. 46, pp.712-721 “ An 0.3-mm Si epitaxial base BiCMOS technology with 37-GHz fmax and 10-V Bceo for RF telecommunication, IEEE Journal of Solid-State Circuits, vol.34, pp.357-366 “CMOS Technology - Year 2010 and beyond” Solid-State Electronics, vol.43, pp.543-546 “Single-gate 0.15 and 0.12 mm CMOS with Co salicide technology,” ●1998年発表 1998年6月 ELECTRON DEVICES VOL.45,No.6 High Performance of Silicided Silicon-Sidewall Source and Drain (S⁴D)Structure 1998年6月 ELECTRON DEVICES VOL.45,No.6 High Efficiency and High Linearity InGaP/GaAs HBT Power Amplifiers： Matching Techniques of Source and Load Impedance to Improve Phase Distortion and Linearity 1998年3月 ELECTRON DEVICES VOL.45,No.3 0.15-nm RF CMOS Technology Compatible with Logic CMOS for Low-Voltage Operation 1998年3月 ELECTRON DEVICES VOL.45,No.3 0.15-nm Buried-Channel p-MOSFET's with Ultrathin Boron-Doped Epitaxial Si Layer 1998年3月 ELECTRON DEVICES VOL.45,No.3 Updoped Epitaxial Si Channel n-MOSFET Grown by UHV-CVD with Preheating 1998年3月 ELECTRON DEVICES VOL.45,No.3 Study of Manufacturing Feasiblity of 1.5-nm Direct-Tunneling Gate Oxide MOSFET's: Uniformity, Reliability, and Dopant Penetration of the Gate Oxide Microelectronics Reliability, vol.38, pp.1413-1423 “Application of direct-tunneling gate oxides to high-performance CMOS,” IEEE Trans. Electron Devices, vol. 45, pp.1295-1299 (1998) “High performance of silicided silicon-sidewall source and drain (S4D) structure,” Microelectronics Journal, vol.29, pp.671-678 “Downsizing of silicon MOSFETs beyond 0.1 mm,” IEEE Trans. Electron Devices, vol. 45, pp.737-742 ”0.15-mm RF CMOS technology compatible with logic CMOS for low-voltage operation” IEEE Trans. Electron Devices, vol. 45, pp.717-721 ”A 0.15-mm buried-channel p-MOSFET’s with ultrathin boron-doped epitaxial Si layer,” IEEE Trans. Electron Devices, vol. 45, pp.710-716 ”Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating,” IEEE Trans. Electron Devices, vol. 45, pp.691-700 ”Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFET’s: Uniformity, reliability, and dopant penetration of the gate oxide,” IEICE Trans. on Fundamentals, vol.E81-A, pp.382-388 “A 1.5GHZ CMOS low noise amplifier” ●1997年発表 1997年11月 ELECTRON DEVICES VOL.44,No.11 A Hot-Carrier Degradation Mechanism and Electrical Characteristics in S⁴D n-MOSFET's IEEE Trans. Electron Devices, vol. 44, pp.2053-2058 “A hot-carrier degradation mechanism and electrical charateristics in of S4D n-MOSFETs,” Microelectronic Engineering, vol.39 pp.7-30 “Technology toward low power / low voltage and scaling of MOSFETs” Solid-State Electronics Vol.41, pp. 707-714 "Prospects for Low-power, High-speed MPUs Using 1.5 nm Direct-tunneling Gate Oxide MOSFETs," IEEE Trans. Electron Devices, vol. 43, pp.1233-1242, "1.5 nm Direct-Tunneling Gate Oxide Si MOSFET's," ●1996年発表 Electronics and Communication in Japan, Part 2, vol.79, pp.67-76 ”Realization of High-Performance MOSFETs with gate lengths of 0.1 mm or Less,” Electronics and Communication in Japan, Part 2, vol.79, pp.67-76 (1996) ”Realization of High-Performance MOSFETs with gate lengths of 0.1 mm or Less,” ●1995年発表 IEEE Trans. Electron Devices, vol. 42, pp.1822-1830 "A 40 nm gate length n-MOSFET," IEEE Trans. Electron Devices, vol. 42, pp.1510-1521 "A Study on Hot Carrier Effects on N-MOSFET's Under High Substrate Impurity Concentration," J. Vac. Sci. Technol., vol.B13, pp.1740-1743 M"Fabrication of sub-50-nm gate length n-metal-oxide semiconductor field effect transistors and their electrical characteristics," Microelectronic Engineering, vol.28 pp.147-154 "The future of ultra-small-geometry MOSFETs beyond 0.1 micron," IEEE Trans. Electron Devices, vol. 42, pp.915-922 "Self-Aligned Nickel-Mono-Silicide Technology for High-Speed Deep Submicrometer Logic CMOS ULSI," IEEE Trans. Electron Devices, vol. 42, pp.704-712 "An Improvement of Hot-Carrier Reliability in the Stacked Nitride-Oxide Gate n- and p-MISFET's," IEEE Trans. Electron Devices, vol. 42, pp.399-405 "Sub-20 ps High-Speed ECL Bipolar Transistor with Low Parasitic Architecture," ●1994年発表 IEEE Trans. Electron Devices, vol. 41, pp.2305-2317 "Analysis of Resistance Behavior in Ti- and Ni- Salicided Polysilicon Films," IEEE Trans. Electron Devices, vol. 41, pp.941-951 "Scaling the MOS transistor below 0.1 mm: methodology, device structures and technology requirements," IEEE Trans. Electron Devices, vol. 41, pp.978-987 (1994) "Analysis of the Temperature Dependence of Hot-Carrier-Induced Degradation in Bipolar Transistors for Bi-CMOS," IEEE Trans. Electron Devices, vol. 41, pp.546-552 (1994) "Electrical Characteristics of Rapid Thermal Nitride-Oxide Gate n- and p-MOSFET's with Less Than 1 Atom% Nitrogen Concentration," ●1993年発表 IEICE Trans. Electron., vol.E77-C, pp.174-178 "Monte Carlo Analysis of Velocity Overshoot Effects in Bipolar Devices with and without an i-Layer," IEICE Trans. Electron., vol.E77-C, pp.124-128 ( 1993). "Mechanical Stress Analysis of Trench Isolation Using a Two-Dimensional Simulation," IEEE Trans. Electron Devices, vol.ED-40, no.12, pp.2264-2272 "P-MOSFET's with Ultra-Shallow Solid-Phase-Diffused Drain Structure Produced by Diffusion from BSG Gate-Sidewall," IEEE Trans. Electron Devices, vol. 40, pp.1768-1779 "New Charge Pumping Method for Determining the Spatial Distribution of Hot-Carrier-Induced Fixed Charge in p-MOSFET's," IEEE Trans. Electron Devices, vol. 40, pp.371-377 "A new contact plug technique for deep-submicron ULSIs employing selective nickel silicidation of polysilicon with a titanium nitride stopper," ●1992年発表 1992年6月 VLSI Symposium on Technology, Siattle, Washington, pp.70-71 "A novel selective Ni3Si contact plug technique for deep-submicron ULSIs," IEEE Trans. Electron Devices, vol.39, pp.648-661 "A study of non-equilibrium diffusion modeling; Application to rapid thermal annealing and advanced bipolar technologies," IEEE Trans. Electron Devices, vol.39, pp.33-40, January "Impurity diffusion behaviors of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5 mm Bi-CMOS process," ●1991年発表 H. Iwai, "Hot carrier induced degradation mode in thin gate insulator dual gate MISFETs,", Edited by W. Eccleston and M. Uren, "Insulating Films on Semiconductors 1991," Adam Hilger, Bristol, Philadelphia and New York, pp.83-92 ●1990年発表 IEEE Trans. Electron Devices, vol.37, pp.1496-1503 "Analysis of gate oxide thickness dependence of hot carrier induced degradation in thin gate oxide nMOSFETs," IEEE Trans. Electron Devices, vol. 37, pp.1487-1495 "Analysis of hot carrier induced degradation mode on PMOSFETs," IEEE Trans. Electron Devices, vol.37, pp.562-568 "Electromigration reliability for tungsten filled via hole structure," ●1989年発表 IEEE Trans. Electron Devices, vol.36, pp.1732-1739 "Interface state generation under long term positive bias temperature stress for a p+ poly gate MOS structure," ●1988年発表 "1.2 mm Bi-CMOS technology with high performance ECL," Solid State Devices, edited by E. Soncini and P. U. Calzolari, Elsevier Science Publishers B. V. (North-Holland), pp.199-202 ●1987年発表 IEEE J. Solid-State Circuits, vol.22, pp.733-740 M "A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines," IEEE Trans. Computer-Aided Design, vol.6, pp.173-184 H. Iwai, M. R. Pinto, C. S. Raffrety, J. E. Oristian, and R. W. Dutton, "Analysis of velocity saturation and other effects on short channel MOS transistor capacitances," ●1985年発表 IEEE Trans. Electron Devices, vol. ED-32, pp.344-356 "A scaleable technique for measurement of intrinsic MOS capacitance with atto Farad resolution," 1985年1月IEEE Electron Device Letters, vol.EDL-6, No.1 "A reply to "Comments to `Small geometry MOS transistor capacitance measurement method using simple on-chip circuits" 1985年3月IEEE Electron Device Letters, vol.EDL-6, No.3, pp.120-122 "Velocity saturation effect on short channel MOS transistor capacitance," ●1984年発表 IEEE Trans. Electron Devices, vol.31, pp.1149-1151 "Comparison of intrinsic gettering and epitaxial wafers in terms of soft error endurance and other characteristics of 64k bit dynamic RAM," 1984年10月IEEE Electron Device Letters, vol.EDL-5, No.10, pp.395-397 "Small geometry MOS transistor capacitance measurement method using simple on-chip circuits," ●1982年発表 IEEE Trans. Electron Devices, vol. 29, pp. 1622-1626 "On-chip capacitance measurement circuits in VLSI structures," IEEE Trans. Electron Devices, vol.29, pp.625-630 "Two-dimensional nature of diffused layers and certain limitations in scaling-down coplanar structure," IEEE Electron Device Letters, vol. EDL-3, No.7, pp.182-184 "The effect of substrate materials on holding time degradation in MOS dynamic RAM," ●1981年発表 IEEE Trans. on Electron Devices, vol.28, pp.574-580 "Two-dimensional computer simulation models for MOSLSI fabrication processes," IEEE Trans. Electron Devices, vol.28, pp116-117 L. M. Dang and H. Iwai, "Modeling of the impurity profile in an ion-implanted layer of an IGFET for the calculation of threshold voltages," ●1980年発表 Japan J. Appl. Phys.vol.19, Suppl. 19-1, pp.107-112 "P-channel versus N-channel in MOS-ICs of submicron channel lengths," Toshiba Review, No.128, pp.35-38 "64k-bit dynamic RAM TMM4164C," ●1979年発表 Japan J. Appl. Phys. vol. M. Konaka, H. Iwai, and Y. Nishi, "Suppression of anomalous drain current in short channel MOSFET," IEEE J. Solid-State Circuits, vol. 14, pp.482-485 "A 64k bit MOS dynamic random access memory," ●1976年発表 Japan J. Appl. Phys., vol.15 pp.63-69 "Micro-probe Auger analysis of Si migration in Al metallization for LSI,"

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