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- Paper List

Iwai Laboratory

Frontier Collaborative Research Center, Tokyo Institute of Technology

- List of Doctoral/Master/Graduation Thesis

Thesis of Earned Doctorate in 2006
NG Jin Aun	A Study on Mobility of MOSFETs with La<sub>2</sub>O<sub>3 Gate Dielectric
Hisayo Momose	Study on si transistors with high performance and high reliability for CMOS/BiCMOS integrated circuits

Thesis of Earned Doctorate in 2005
Yongshik Kim	Analysis of Electrical Conduction in Rare Earth Gate Dielectrics

Thesis of Earned Doctorate in 2004
Jun-ichi Tonotani	Study on Dry Etching for Profile and Selectivity Control in ULSI(Ultra-Large Scale Integrated Circuits) Manufacturing
Kyosuke Ohshima	Application of High Dielectric Constant Thin Film for Advanced CMOS Devices

Thesis of Earned Doctorate in 2003
Shuji Ikeda	Tecnology for High-density and High-performance Static Random Access Memory

Master Thesis in 2007
Yasuhiro Shiino	Novel Rare Earth Oxides Gate Stack for Advanced La<sub>2</sub>O<sub>3-MOSFET
Takashi Shiozawa	Improvement of Thermal Stability of Ni Silicide on Heavily Doped N⁺-Si
Jaeyeol Song	A Study on Process Optimization of Ge-MOS Devices with La<sub>2</sub>O<sub>3 Gate dielectric
Kiichi Tachi	A Study on Process Optimization for High Performance La<sub>2</sub>O<sub>3-MOS devices
Masayuki Nakagawa	Study on RF Characteristics and Modeling of Scaled MOSFET
Koji Nagahiro	Thermal Stability of NiSi Improved by Post Silicidation Metal Doping Method.

Thesis of Earned Doctorate in 2001
Hitoshi Aoki	A study on Accurate and Efficient Compact Models for New Components Used for Integrated Circuits
Masakatsu Tsuchiaki	A study of Si/SiO<sub>2 Interfacial Properties for ULSI Fabrication

Master Thesis in 2006
Issui Aiba	Study of Resist Related Problems and Solid Phase Epitaxial Growth on Plasma Doping Method
Yusuke Kuroki	Novel Gate Stack and Process Optimization for La<sub>2</sub>O<sub>3-MOSFET
Kentaro Nakagawa	Study on Y<sub>2</sub>O<sub>3 Buffer Layer for High-temperature Processed La<sub>2</sub>O<sub>3 MOSFET
Akira Fukuyama	Electrical Characteristics of La<sub>2</sub>O<sub>3 MIM Capacitor with Different Process Condition
Satoshi Yoshizaki	Study on Characterization and Modeling of RF MOSFET
Ruifei Xiang	Formation of Heat Resistant Ni Silicide Using Metal Additive for Nanoscale CMOS

Master Thesis in 2005
Yoichi Kobayashi	Formation of heat resistant Ni silicide by additional Hf layers
Takahisa Sato	Effects of surface treatments on the retained dose of impurities for plasma doping
Henderianshah Sauddin	Low-Frequency (1/f ) Noise of nMISFET with La<sub>2</sub>O<sub>3 High-k Gate Dielectrics and Analysis of Ultra-Shallow p+/n Junction Formed by Plasma Doping Method
Kunihiro Miyauchi	Study on La<sub>2</sub>O<sub>3/Y<sub>2</sub>O<sub>3 Stacked Gate Dielectrics
Joji Yoshida	The Process Dependence of Low-Frequency Noise in MOSFETS with La<sub>2</sub>O<sub>3 Gate Dieletrics

Master Thesis in 2004
Isao Ueda	A study on High-k Stacked GAte Dielectric Thin films of Rare Earth Oxides
Atsushi Kuriyama	Effect of Post Metallization Annealing for La<sub>2</sub>O<sub>3 Thin Film

Master Thesis in 2003
Sadahiro Akama	A study on Stability of High-k Gate Thin Films in Moisture Ambience and Ultra-shallow Junction Technology by Plasma Doping Method
Chizuru Ohshima	A study on the effect of surface treatment of Si substrate on the rare earth gate dielectrics
Ikumi Kashiwagi	A study on dependence of amorphous or crystalline rare earth gate oxides on Si surface orientation
Akira Kikuchi	Study on Fabrication Process for High-k Gate MOSFET Using Rare Earth Oxides
Junichi Taguchi	A study on the effect of the low temperature long time anneal for Dy<sub>2</sub>O<sub>3 and fabrication process of TaN gate electrode
Hiroyuki Yamamoto	A Study on the Ultra-High Vacuum Anneal Method for the Rare Earth Gate Dielectrics

Master Thesis in 2002
Koh-ichiro Satoh	Study on Pr<sub>2</sub>O<sub>3 Dielectric Thin Films for MOSFET Gate Insulator Application
Mitsuhiro Takeda	Study on Lu<sub>2</sub>O<sub>3 Thin Films for High-k Gate Insulator Application

Master Thesis in 2001
Ryosuke Fujimura	Analysis on high-k dielectric gate insulator MISFETs by two-dimensional device